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Product Description
I. INTRODUCTION
Microsis' ARINC429 controller IP core contains a transmitter IP core and a receiver IP core, fully compliant with ARINC429 standard. The IP core could be implemented in FPGA and ASIC. Both the transmitter and receiver have a built-in 32-bit wide configurable FIFO, which is used to store ARINC429 data word. The receiver could filter the receiving data word, according to the SDI field and/or LABEL fields of the receiving data word.
The ARINC429 IP core could interface with nowadays popular ARINC429 bus line driver and Receivers.
II. FEATURE
2.1. Supports ARINC Specification 429-16.
2.2. Independent Transmitter and Receiver.
2.3. Programmable FIFO Depth
Up to 512 Words
2.4. Programmable FIFO Interrupt Generation
FIFO interrupt Condition is Programmable via "FIFO_threshold" register.
2.5. Internal, Wrap-Around Testing.
2.6. Programmable Baud Rate on Each Channel
At Any Baud Rate, 12.5 or 100 KHz is Recommended.
2.7. CPU Interface
Provides Direct CPU Access.
Support 32-bit, 16-bit and 8-bit host interface.
2.8. Line driver interface
Supports Nowadays Popular Line Drivers and Receivers.
III. SUPPORTED FPGA DEVICES
3.1. ALTERA CYLONEI/II/III and STRATIX.
3.2. XILINX SPARTAN and VIRTEX.
3.3. ACTEL PROASIC.
AVAILABLE
4.1. FPGA netlist.
4.2. ASIC netlist.
4.3. RTL source code.
Microsis' ARINC429 controller IP core contains a transmitter IP core and a receiver IP core, fully compliant with ARINC429 standard. The IP core could be implemented in FPGA and ASIC. Both the transmitter and receiver have a built-in 32-bit wide configurable FIFO, which is used to store ARINC429 data word. The receiver could filter the receiving data word, according to the SDI field and/or LABEL fields of the receiving data word.
The ARINC429 IP core could interface with nowadays popular ARINC429 bus line driver and Receivers.
II. FEATURE
2.1. Supports ARINC Specification 429-16.
2.2. Independent Transmitter and Receiver.
2.3. Programmable FIFO Depth
Up to 512 Words
2.4. Programmable FIFO Interrupt Generation
FIFO interrupt Condition is Programmable via "FIFO_threshold" register.
2.5. Internal, Wrap-Around Testing.
2.6. Programmable Baud Rate on Each Channel
At Any Baud Rate, 12.5 or 100 KHz is Recommended.
2.7. CPU Interface
Provides Direct CPU Access.
Support 32-bit, 16-bit and 8-bit host interface.
2.8. Line driver interface
Supports Nowadays Popular Line Drivers and Receivers.
III. SUPPORTED FPGA DEVICES
3.1. ALTERA CYLONEI/II/III and STRATIX.
3.2. XILINX SPARTAN and VIRTEX.
3.3. ACTEL PROASIC.
AVAILABLE
4.1. FPGA netlist.
4.2. ASIC netlist.
4.3. RTL source code.
Address:
Building Six, No. 1, Pingdong 6th Road, Nanping High-Tech Industry Park, Zhuhai, Guangdong, China
Business Type:
Manufacturer/Factory, Other
Business Range:
Electrical & Electronics, Service
Main Products:
Test Analyze, IP core, Simulation
Company Introduction:
Zhuhai Mircosis Electronic Technology Co., Ltd focuses on developing test/measurement products and high-reliability system. Base on "ANYTEST" platform technology, we′ve developed series of test/measure instruments/equipments. AT15XXX series products is a package of MIL-STD-1553A/B bus test solution. Since brought to market, it′s been welcomed by users for its detailed and user-friendly design. With the help of AT15XXX, the 1553B bus products test is no longer complicate. Base on our long-term technique deposition of high-reliability IP cores, including peripheral IP cores, bus controller IP cores and microprocessor IP cores, we would provide customers a package of high-reliability embedded computer solutions. Such a solution could be implemented in an FPGA or in an ASIC chip. With this solution, he volume of the computer would be minimized greatly, and the reliability would be improved highly.
