Product Description
Company Info
Product Description
I. INTRODUCTION
EBR-1533 is the Enhanced Bit Rate version of MIL-STD-1553A/B, which is defined by SAE according to MIL-STD-1553B standard. Different from MIL-STD-1553B bus, EBR-1553 applies star-topology and use RS485 as physical layer. Except the RT to RT message format, EBR-1553 supports all the other message formats defined by MIL-STD-1553B.
Since EBR-1553 applies start-topology, a HUB should be used to route messages from an RT to the BC or from the BC to an RT. AS5652 defines three types of HUBs, "SPEC" mode "SWITCH" mode and "LINK" mode.
Under SPEC mode, BC sends the message to all of the RTs, and then monitors the Tx data line of all the RTs'. The same with MIL-STD-1553B, when a command word received, an RT would only response the command word which contains its own address in the RT address field.
Under SWITCH mode, BC assign each node with an universal address, ranging from 0 to 31. For each RT, it should be placed at the designated node, which the address is the same with the RT. For example, the RT 8 should only be placed at the node 8. Unlike the SPEC mode, under SWITCH mode, the BC only send the message to the RT addressed by the command word.
The address field of the command word will no make any sense, when the HUB work under LINK mode. The BC will only send the command to the RT intended. For example, if the BC want to send a command to RT8, it only send the command to the node 8, the address field of the command word is all zero, and the RT8 will response to all the incoming command except the broadcast.
II. FBIP151X INTRODUCTION
Zhuhai Microsis Electronic Technology Co., Ltd has developed two IP cores, FBIP1511 and FBIP1512, which could provide total EMR-1553 solution. FBIP1511 is a Bus Controller IP core with a built-in SWITCH mode HUB, and up to 32 RTs and 1 BM could be connected. FBIP1512 is a RT/BM IP core with 1 RT and 1 BM. The function and register operation of FBIP151X is compatible with BU6158X.
FBIP151X could be implemented in ALTERA CYCLONEI/II/II FPGA, achieving 160MHz sampling clockthat makes the Codec more stable and reliable.
2.1. FBIP1511
2.1.1. Functional block diagram.
Figure 1 FBIP1511 functional block diagram
2.1.2. Features
2.1.2.1. Supports EBR-1553 bit rate, up to 10Mbps.
2.1.2.2. Conform to MIL-STD-1553A/B bus protocol, and supports all the MIL-STD-1553A/B message format except RT2RT format.
2.1.2.3. Register operation and memory layout are compatible with DDC BU6158X.
2.1.2.4. Built-in HUB, which supports up to 33 dual redundant interfaces, 1 dedicated BM interface, 32 standard interface for RTs, which support standard RS485 transceiver.
2.1.2.5. Standard parallel host interfaces, 16-bit/8-bit data width supported.
2.1.2.6. Coded in VHDL, which can be implemented in both the FPGA and the ASIC.
2.1.2.7. Fault-tolerant design, which could tolerant 1-bit upset of memory or register.
2.1.3. MISC
Bus waveforms are shown as figure 6 to 10.
2.2. FBIP1512
2.2.1. Functional block diagram
Figure 2 FBIP1512 functional block diagram
2.2.2. Features
2.2.2.1. Supports EBR-1553 bit rate, up to 10Mbps.
2.2.2.2. Conform to MIL-STD-1553A/B bus protocol, and supports all the MIL-STD-1553A/B message format except RT2RT format.
2.2.2.3. Registers operation and memory layout are compatible with DDC BU6158X...
2.2.2.4.1 BM and 1 RT are implemented in the FBIP1512, which can be configured as a RT or a BM through register configuration.
2.2.2.5. Provides a dual redundant transceiver interface, which supports standard RS485 transceiver.
2.2.2.6. Stand paraller host interfaces, 16-bit/8-bit data width.
2.2.2.7. Coded in VHDL, which can be implemented in both the FPGA and the ASI.
2.2.2.8. Fault-tolerant design, which could tolerant 1-bit upset of memory or register.
2.2.3. MISC
Bus waveforms are shown as figure 6 to 10...
EBR-1533 is the Enhanced Bit Rate version of MIL-STD-1553A/B, which is defined by SAE according to MIL-STD-1553B standard. Different from MIL-STD-1553B bus, EBR-1553 applies star-topology and use RS485 as physical layer. Except the RT to RT message format, EBR-1553 supports all the other message formats defined by MIL-STD-1553B.
Since EBR-1553 applies start-topology, a HUB should be used to route messages from an RT to the BC or from the BC to an RT. AS5652 defines three types of HUBs, "SPEC" mode "SWITCH" mode and "LINK" mode.
Under SPEC mode, BC sends the message to all of the RTs, and then monitors the Tx data line of all the RTs'. The same with MIL-STD-1553B, when a command word received, an RT would only response the command word which contains its own address in the RT address field.
Under SWITCH mode, BC assign each node with an universal address, ranging from 0 to 31. For each RT, it should be placed at the designated node, which the address is the same with the RT. For example, the RT 8 should only be placed at the node 8. Unlike the SPEC mode, under SWITCH mode, the BC only send the message to the RT addressed by the command word.
The address field of the command word will no make any sense, when the HUB work under LINK mode. The BC will only send the command to the RT intended. For example, if the BC want to send a command to RT8, it only send the command to the node 8, the address field of the command word is all zero, and the RT8 will response to all the incoming command except the broadcast.
II. FBIP151X INTRODUCTION
Zhuhai Microsis Electronic Technology Co., Ltd has developed two IP cores, FBIP1511 and FBIP1512, which could provide total EMR-1553 solution. FBIP1511 is a Bus Controller IP core with a built-in SWITCH mode HUB, and up to 32 RTs and 1 BM could be connected. FBIP1512 is a RT/BM IP core with 1 RT and 1 BM. The function and register operation of FBIP151X is compatible with BU6158X.
FBIP151X could be implemented in ALTERA CYCLONEI/II/II FPGA, achieving 160MHz sampling clockthat makes the Codec more stable and reliable.
2.1. FBIP1511
2.1.1. Functional block diagram.
Figure 1 FBIP1511 functional block diagram
2.1.2. Features
2.1.2.1. Supports EBR-1553 bit rate, up to 10Mbps.
2.1.2.2. Conform to MIL-STD-1553A/B bus protocol, and supports all the MIL-STD-1553A/B message format except RT2RT format.
2.1.2.3. Register operation and memory layout are compatible with DDC BU6158X.
2.1.2.4. Built-in HUB, which supports up to 33 dual redundant interfaces, 1 dedicated BM interface, 32 standard interface for RTs, which support standard RS485 transceiver.
2.1.2.5. Standard parallel host interfaces, 16-bit/8-bit data width supported.
2.1.2.6. Coded in VHDL, which can be implemented in both the FPGA and the ASIC.
2.1.2.7. Fault-tolerant design, which could tolerant 1-bit upset of memory or register.
2.1.3. MISC
Bus waveforms are shown as figure 6 to 10.
2.2. FBIP1512
2.2.1. Functional block diagram
Figure 2 FBIP1512 functional block diagram
2.2.2. Features
2.2.2.1. Supports EBR-1553 bit rate, up to 10Mbps.
2.2.2.2. Conform to MIL-STD-1553A/B bus protocol, and supports all the MIL-STD-1553A/B message format except RT2RT format.
2.2.2.3. Registers operation and memory layout are compatible with DDC BU6158X...
2.2.2.4.1 BM and 1 RT are implemented in the FBIP1512, which can be configured as a RT or a BM through register configuration.
2.2.2.5. Provides a dual redundant transceiver interface, which supports standard RS485 transceiver.
2.2.2.6. Stand paraller host interfaces, 16-bit/8-bit data width.
2.2.2.7. Coded in VHDL, which can be implemented in both the FPGA and the ASI.
2.2.2.8. Fault-tolerant design, which could tolerant 1-bit upset of memory or register.
2.2.3. MISC
Bus waveforms are shown as figure 6 to 10...
Address:
Building Six, No. 1, Pingdong 6th Road, Nanping High-Tech Industry Park, Zhuhai, Guangdong, China
Business Type:
Manufacturer/Factory, Other
Business Range:
Electrical & Electronics, Service
Main Products:
Test Analyze, IP core, Simulation
Company Introduction:
Zhuhai Mircosis Electronic Technology Co., Ltd focuses on developing test/measurement products and high-reliability system. Base on "ANYTEST" platform technology, we′ve developed series of test/measure instruments/equipments. AT15XXX series products is a package of MIL-STD-1553A/B bus test solution. Since brought to market, it′s been welcomed by users for its detailed and user-friendly design. With the help of AT15XXX, the 1553B bus products test is no longer complicate. Base on our long-term technique deposition of high-reliability IP cores, including peripheral IP cores, bus controller IP cores and microprocessor IP cores, we would provide customers a package of high-reliability embedded computer solutions. Such a solution could be implemented in an FPGA or in an ASIC chip. With this solution, he volume of the computer would be minimized greatly, and the reliability would be improved highly.
